EP1810LC-25 vs EP1810LC-20T Comparison

Detailed side-by-side comparison of EP1810LC-25 by Altera and EP1810LC-20T by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP1810LC-25 EP1810LC-20T
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $8.40 $9.95
Product Family Altera Classic EPLD —
Part Number EP1810LC-25 —
Macrocells 48 48
Propagation Delay (tPD) 25 ns —
Dedicated Inputs 12 —
I/O Pins 48 —
External Clock Inputs 4 —
Supply Voltage (VCC) 5 V (TTL-compatible) 5 V
Operating Mode Turbo-only (no slow-power mode) —
Package 68-pin JLCC (J-leaded ceramic chip carrier) —
Package Code LC = 68-pin JLCC —
Mounting Type Surface Mount Surface Mount (socket-compatible)
Technology CMOS EPLD (erasable programmable logic device) —
Programmable Interconnect Global + Local buses —
Programming Method Altera Classic programmer + MAX+PLUS II legacy flow —
Lifecycle Status Obsolete (legacy Altera Classic family) —
RoHS Status [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] Non-compliant (legacy 5V PLCC)
Operating Temperature [DATA_NEEDED: temperature grade for LC package] 0C to +70C (commercial)
Family — Altera Classic EPLD
Product Type — CPLD (Complex Programmable Logic Device)
Usable Gates — 900 gates
Logic Array Blocks (LABs) — 4 x 12 macrocells
Maximum Toggle Frequency — 50 MHz
Pin-to-Pin Logic Delay (tPD) — 20 ns
Package Type — PLCC-68 (J-lead)
Configuration Memory — On-chip EEPROM (non-volatile)
Programming Interface — JTAG (IEEE 1149.1) and Altera Master/Slave serial
Shipping Format — Tape & Reel ("T" suffix)

Datasheets & Resources

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