EP1810LC-25 vs EP1810LI-25 Comparison

Detailed side-by-side comparison of EP1810LC-25 by Altera and EP1810LI-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP1810LC-25 EP1810LI-25
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $8.40 $9.95
Product Family Altera Classic EPLD —
Part Number EP1810LC-25 —
Macrocells 48 48
Propagation Delay (tPD) 25 ns 25 ns
Dedicated Inputs 12 12
I/O Pins 48 48
External Clock Inputs 4 —
Supply Voltage (VCC) 5 V (TTL-compatible) 4.5 V to 5.5 V (nominal 5 V)
Operating Mode Turbo-only (no slow-power mode) —
Package 68-pin JLCC (J-leaded ceramic chip carrier) 68-pin PLCC (J68, J-Lead)
Package Code LC = 68-pin JLCC —
Mounting Type Surface Mount —
Technology CMOS EPLD (erasable programmable logic device) —
Programmable Interconnect Global + Local buses —
Programming Method Altera Classic programmer + MAX+PLUS II legacy flow —
Lifecycle Status Obsolete (legacy Altera Classic family) —
RoHS Status [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] unknown
Operating Temperature [DATA_NEEDED: temperature grade for LC package] —
Family — Altera Classic EPLD
Device Type — EPLD (Erasable Programmable Logic Device), UV-erasable / OTP
Usable Gates — 900
Maximum Counter Frequency — 40 MHz
Global Clock Inputs — 4
Interconnect — Programmable global and local buses
JESD-30 Package Code — S-PQCC-J68
Process Technology — CMOS
Operating Temperature (Industrial 'I' suffix) — -40 C to +85 C
Programming Mode — EPROM/UV-erasable (windowed) and OTP
Development Tool — Altera MAX+PLUS II
Lead-Free Status — unknown

Datasheets & Resources

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