EP1810LC-25 vs EP1810LI-25 Comparação

Comparação detalhada lado a lado de EP1810LC-25 por Altera e EP1810LI-25 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.

Comparação de especificações

Parâmetro EP1810LC-25 EP1810LI-25
Marca Altera Altera
Categoria FPGA & CPLD FPGA & CPLD
Status do ciclo de vida Obsolete Obsolete
Status do estoque In Stock In Stock
Preço unitário (USD) $8,40 $9,95
Product Family Altera Classic EPLD —
Part Number EP1810LC-25 —
Macrocells 48 48
Propagation Delay (tPD) 25 ns 25 ns
Dedicated Inputs 12 12
I/O Pins 48 48
External Clock Inputs 4 —
Supply Voltage (VCC) 5 V (TTL-compatible) 4.5 V to 5.5 V (nominal 5 V)
Operating Mode Turbo-only (no slow-power mode) —
Encapsulamento 68-pin JLCC (J-leaded ceramic chip carrier) 68-pin PLCC (J68, J-Lead)
Package Code LC = 68-pin JLCC —
Tipo de montagem Surface Mount —
Technology CMOS EPLD (erasable programmable logic device) —
Programmable Interconnect Global + Local buses —
Programming Method Altera Classic programmer + MAX+PLUS II legacy flow —
Status do ciclo de vida Obsolete (legacy Altera Classic family) —
Status RoHS [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] unknown
Temperatura de operação [DATA_NEEDED: temperature grade for LC package] —
Family — Altera Classic EPLD
Device Type — EPLD (Erasable Programmable Logic Device), UV-erasable / OTP
Usable Gates — 900
Maximum Counter Frequency — 40 MHz
Global Clock Inputs — 4
Interconnect — Programmable global and local buses
JESD-30 Package Code — S-PQCC-J68
Process Technology — CMOS
Operating Temperature (Industrial 'I' suffix) — -40 C to +85 C
Programming Mode — EPROM/UV-erasable (windowed) and OTP
Development Tool — Altera MAX+PLUS II
Lead-Free Status — unknown

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