EP1810LC-25T vs EP1810LC-30 Comparison
Detailed side-by-side comparison of EP1810LC-25T by Intel and EP1810LC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1810LC-25T | EP1810LC-30 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.40 | $9.95 |
| Family | Altera Classic EP1810 | Altera Classic EPLD |
| Device Type | EPLD (Erasable/OTP Complex PLD) | — |
| Macrocells | 48 (4 quadrants x 12 macrocells) | 48 |
| Usable Gates | Approx. 900 | — |
| Dedicated Inputs | 16 | — |
| Bidirectional I/O Pins | 48 | — |
| External Clocks | 4 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 5 V nominal | — |
| Operating Temperature | 0 °C to +70 °C (commercial) | [DATA_NEEDED: temperature grade] |
| Package | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) | JLCC-68 (68-pin J-Lead ceramic chip carrier) |
| Mounting Type | Surface Mount | — |
| Technology | CMOS, UV-erasable / OTP | CMOS, low-power (LC) |
| I/O Standard | TTL-compatible 5 V | — |
| RoHS Status | [DATA_NEEDED: RoHS status - confirm with manufacturer] | unknown (legacy ceramic package) |
| Programming Tool | Altera MAX+PLUS II / Quartus Classic | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Flip-Flops | — | 48 (one per macrocell) |
| Speed Grade (tPD) | — | 30 ns |
| Supply Voltage | — | 5 V (typical) |
| Programming | — | Device programmer or JTAG |
| Standby Current | — | [DATA_NEEDED: ICC standby] |
| Number of Pins | — | 68 |
| Number of I/O Pins | — | [DATA_NEEDED: I/O count] |
| Logic Blocks | — | 48 macrocells |