EP20K1000CF33C8ES vs EP20K1000CF33C9ES Comparison

Detailed side-by-side comparison of EP20K1000CF33C8ES by Intel and EP20K1000CF33C9ES by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EP20K1000CF33C9ES EP20K1000CF33C9ES - APEX-20KC FPGA 1M Gates 38400 LE 1020-FBGA

EP20K1000CF33C9ES - APEX-20KC FPGA 1M Gates 38400 LE 1020-FBGA

EP20K1000CF33C9ES ⚠ Last Time Buy

Specification Comparison

Parameter EP20K1000CF33C8ES EP20K1000CF33C9ES
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $155.00 $215.00
Series APEX 20KC β€”
Family APEX (Advanced Programmable Embedded Matrix) APEX-20KC
System Gates 1,000,000 β€”
Logic Elements / Cells 38,400 β€”
Embedded Memory Bits 327,680 β€”
Maximum User I/O 708 β€”
Package 1020-ball FC-FBGA (Flip-Chip Fine-pitch BGA) 1,020-ball FineLine BGA (FBGA)
Mounting Type Surface Mount (BGA) β€”
Core Supply Voltage 1.8 V β€”
Process Technology 0.15 Β΅m CMOS 0.18 um CMOS
Maximum Toggle Frequency 301.21 MHz β€”
Speed Grade C8 (Commercial) C9
Architecture MultiCore (LUT + Embedded System Blocks) β€”
Number of PLLs 4 β€”
Operating Temperature 0 Β°C to +85 Β°C (Commercial) 0 C to +85 C (commercial)
Programming Interface JTAG (IEEE 1149.1) - serial via Altera Quartus β€”
Embedded System Blocks (ESBs) Dual-port RAM / ROM / CAM 212
RoHS Status unknown [DATA_NEEDED: RoHS compliance status]
Lead-Free unknown [DATA_NEEDED: lead-free finish status]
Manufacturer β€” Intel (formerly Altera)
Typical Gate Count β€” 1,000,000 system gates
Logic Elements β€” 38,400
Logic Array Blocks (LABs) β€” 3,840
Total Embedded RAM Bits β€” 327,680 bits
Maximum User I/O Pins β€” 708
Logic Element Architecture β€” 4-input LUT with dedicated carry chain
Maximum Embedded RAM per ESB β€” 32,768 bits (dual-port, FIFO support)
Phase-Locked Loops β€” Up to 4 enhanced PLLs
MultiVolt I/O Support β€” 1.8V / 2.5V / 3.3V / 5.0V
JTAG Support β€” IEEE 1149.1 boundary-scan
Configuration Method β€” Passive serial / Passive parallel / JTAG

Datasheets & Resources

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