EP20K1000CF33C8ES vs EP20K1000CF33C9ES Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP20K1000CF33C8ES disebabkan oleh Intel dan EP20K1000CF33C9ES disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EP20K1000CF33C9ES - APEX-20KC FPGA 1M Gates 38400 LE 1020-FBGA
EP20K1000CF33C9ES ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EP20K1000CF33C8ES | EP20K1000CF33C9ES |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Masa Terakhir Dibeli |
| Series | APEX 20KC | — |
| Family | APEX (Advanced Programmable Embedded Matrix) | APEX-20KC |
| System Gates | 1,000,000 | — |
| Logic Elements / Cells | 38,400 | — |
| Embedded Memory Bits | 327,680 | — |
| Maximum User I/O | 708 | — |
| Kemasan | 1020-ball FC-FBGA (Flip-Chip Fine-pitch BGA) | 1,020-ball FineLine BGA (FBGA) |
| Jenis Pemasangan | Surface Mount (BGA) | — |
| Core Supply Voltage | 1.8 V | — |
| Process Technology | 0.15 µm CMOS | 0.18 um CMOS |
| Maximum Toggle Frequency | 301.21 MHz | — |
| Speed Grade | C8 (Commercial) | C9 |
| Architecture | MultiCore (LUT + Embedded System Blocks) | — |
| Number of PLLs | 4 | — |
| Suhu Operasi | 0 °C to +85 °C (Commercial) | 0 C to +85 C (commercial) |
| Programming Interface | JTAG (IEEE 1149.1) - serial via Altera Quartus | — |
| Embedded System Blocks (ESBs) | Dual-port RAM / ROM / CAM | 212 |
| Status RoHS | unknown | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | unknown | [DATA_NEEDED: lead-free finish status] |
| Manufacturer | — | Intel (formerly Altera) |
| Typical Gate Count | — | 1,000,000 system gates |
| Logic Elements | — | 38,400 |
| Logic Array Blocks (LABs) | — | 3,840 |
| Total Embedded RAM Bits | — | 327,680 bits |
| Maximum User I/O Pins | — | 708 |
| Logic Element Architecture | — | 4-input LUT with dedicated carry chain |
| Maximum Embedded RAM per ESB | — | 32,768 bits (dual-port, FIFO support) |
| Phase-Locked Loops | — | Up to 4 enhanced PLLs |
| MultiVolt I/O Support | — | 1.8V / 2.5V / 3.3V / 5.0V |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Configuration Method | — | Passive serial / Passive parallel / JTAG |