EP20K100EBC652-2X vs EP20K200EBC652-2X Comparison
Detailed side-by-side comparison of EP20K100EBC652-2X by Altera and EP20K200EBC652-2X by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K100EBC652-2X | EP20K200EBC652-2X |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $85.00 | $195.00 |
| Family | APEX 20KE | APEX-20KE |
| Typical Gates | 100,000 | โ |
| Maximum System Gates | 263,000 | โ |
| Logic Elements | 4,160 | โ |
| Embedded System Blocks (ESBs) | 26 | โ |
| Maximum RAM Bits | 53,248 | โ |
| Maximum User I/O Pins | 246 | โ |
| Supply Voltage - Core | 1.8 V | โ |
| Supply Voltage - I/O | 1.8 V / 2.5 V / 3.3 V | โ |
| Package | 652-ball BGA (EBC652) | 652-BGA |
| Speed Grade | -2 (faster commercial) | โ |
| Process Technology | 0.18 ยตm CMOS, SRAM-based | 0.18 um CMOS |
| Operating Temperature | 0C to +85C (commercial) | โ |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Method | Passive Serial / Passive Parallel / JTAG (EPC) | Serial or Parallel PROM, JTAG (IEEE 1149.1) |
| Clock Resources | Up to 4 DLLs, multiple global clocks | โ |
| RoHS Status | [DATA_NEEDED: RoHS status] | โ |
| Series | โ | APEX-20KEยฎ |
| Device Logic Elements | โ | 8,320 |
| Number of LABs/CLBs | โ | 832 |
| Total RAM Bits | โ | 106,496 |
| Number of I/O Pins | โ | 376 |
| Number of Gates | โ | 200,000 (typical) |
| Core Supply Voltage | โ | 1.71 V to 1.89 V (1.8 V nominal) |
| Operating Temperature (TJ) | โ | 0C to +85C |
| I/O Standard Support | โ | LVTTL, LVCMOS, LVDS, PCI, GTL+, SSTL |
| Lead-Free / RoHS | โ | Compliant (per DigiKey listing) |