EP20K100EBC652-2X vs EP20K200EBC652-2X 对比
详细并排对比 EP20K100EBC652-2X 出自 Altera 和 EP20K200EBC652-2X 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP20K100EBC652-2X | EP20K200EBC652-2X |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $85.00 | $195.00 |
| Family | APEX 20KE | APEX-20KE |
| Typical Gates | 100,000 | — |
| Maximum System Gates | 263,000 | — |
| Logic Elements | 4,160 | — |
| Embedded System Blocks (ESBs) | 26 | — |
| Maximum RAM Bits | 53,248 | — |
| Maximum User I/O Pins | 246 | — |
| Supply Voltage - Core | 1.8 V | — |
| Supply Voltage - I/O | 1.8 V / 2.5 V / 3.3 V | — |
| 封装 | 652-ball BGA (EBC652) | 652-BGA |
| Speed Grade | -2 (faster commercial) | — |
| Process Technology | 0.18 µm CMOS, SRAM-based | 0.18 um CMOS |
| 工作温度 | 0C to +85C (commercial) | — |
| 安装类型 | Surface Mount | Surface Mount |
| Configuration Method | Passive Serial / Passive Parallel / JTAG (EPC) | Serial or Parallel PROM, JTAG (IEEE 1149.1) |
| Clock Resources | Up to 4 DLLs, multiple global clocks | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | — |
| Series | — | APEX-20KE® |
| Device Logic Elements | — | 8,320 |
| Number of LABs/CLBs | — | 832 |
| Total RAM Bits | — | 106,496 |
| Number of I/O Pins | — | 376 |
| Number of Gates | — | 200,000 (typical) |
| Core Supply Voltage | — | 1.71 V to 1.89 V (1.8 V nominal) |
| Operating Temperature (TJ) | — | 0C to +85C |
| I/O Standard Support | — | LVTTL, LVCMOS, LVDS, PCI, GTL+, SSTL |
| Lead-Free / RoHS | — | Compliant (per DigiKey listing) |