EP20K400FC672-3 vs EP20K400FI672-2N Comparison
Detailed side-by-side comparison of EP20K400FC672-3 by Altera and EP20K400FI672-2N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400FC672-3 | EP20K400FI672-2N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | APEX 20K | APEX 20K |
| Device Logic Elements | 16,640 cells | — |
| Typical Gate Count | 400,000 system gates | — |
| Maximum User I/Os | 502 | — |
| Propagation Delay | 2.5 ns | 3.1 ns |
| Internal Performance | 167 MHz | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Core Supply Voltage | 2.5 V | — |
| Logic Family | CMOS, SRAM-based | — |
| Package | 672-pin FC-FBGA | 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA) |
| Package Code | BGA | — |
| Number of Terminals | 672 | — |
| Terminal Form | Ball (BGA) | — |
| Speed Grade | -3 (commercial fastest) | -2 |
| Operating Temperature | 0 °C to 85 °C | Commercial (0 °C to +70 °C) [DATA_NEEDED: industrial variant] |
| Mounting Type | Surface Mount | Surface Mount |
| Architecture | MultiCore (LUT + Embedded System Blocks) | — |
| Programming Method | SRAM, JTAG (ByteBlaster) | — |
| Lifecycle Status | Obsolete / Legacy | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant (lead-free) |
| Typical Gates | — | 400,000 |
| Logic Elements / Cells | — | 16,640 |
| Maximum User I/O | — | 488 |
| Embedded Memory Bits | — | 212,992 bits |
| Embedded Array Blocks (EABs) | — | [DATA_NEEDED: EAB count per family datasheet] |
| Core Voltage | — | 2.5 V |
| Maximum Frequency | — | 200 MHz |
| Package Body Size | — | 27 x 27 mm |
| Terminal Pitch | — | 1.0 mm |
| Moisture Sensitivity Level (MSL) | — | 3 |
| Peak Reflow Temperature | — | 220 °C |
| Configuration Modes | — | PS, PPS, PPA, JTAG |
| Supported I/O Standards | — | LVTTL, LVCMOS, SSTL, HSTL |