EP20K400FC672-3 vs EP20K400FI672-2N 对比

详细并排对比 EP20K400FC672-3 出自 Altera 和 EP20K400FI672-2N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400FC672-3 EP20K400FI672-2N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $138.00 $188.75
Family APEX 20K APEX 20K
Device Logic Elements 16,640 cells —
Typical Gate Count 400,000 system gates —
Maximum User I/Os 502 —
Propagation Delay 2.5 ns 3.1 ns
Internal Performance 167 MHz —
Process Technology 0.22 µm CMOS 0.22 µm CMOS
Core Supply Voltage 2.5 V —
Logic Family CMOS, SRAM-based —
封装 672-pin FC-FBGA 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA)
Package Code BGA —
Number of Terminals 672 —
Terminal Form Ball (BGA) —
Speed Grade -3 (commercial fastest) -2
工作温度 0 °C to 85 °C Commercial (0 °C to +70 °C) [DATA_NEEDED: industrial variant]
安装类型 Surface Mount Surface Mount
Architecture MultiCore (LUT + Embedded System Blocks) —
Programming Method SRAM, JTAG (ByteBlaster) —
生命周期状态 Obsolete / Legacy —
RoHS 状态 [DATA_NEEDED: RoHS status] Compliant (lead-free)
Typical Gates — 400,000
Logic Elements / Cells — 16,640
Maximum User I/O — 488
Embedded Memory Bits — 212,992 bits
Embedded Array Blocks (EABs) — [DATA_NEEDED: EAB count per family datasheet]
Core Voltage — 2.5 V
Maximum Frequency — 200 MHz
Package Body Size — 27 x 27 mm
Terminal Pitch — 1.0 mm
湿敏等级(MSL) — 3
Peak Reflow Temperature — 220 °C
Configuration Modes — PS, PPS, PPA, JTAG
Supported I/O Standards — LVTTL, LVCMOS, SSTL, HSTL

数据手册与资源

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