EP20K400FI672-2X vs EP20K400FI672-2N Comparison
Detailed side-by-side comparison of EP20K400FI672-2X by Intel and EP20K400FI672-2N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400FI672-2X | EP20K400FI672-2N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $171.00 | $188.75 |
| Family | APEX 20K | APEX 20K |
| Logic Elements | 16,640 | β |
| Typical Gates | 400,000 system gates | 400,000 |
| Embedded Memory | 212,992 bits | β |
| User I/O Pins | 496 | β |
| Package | 672-ball BGA (FI672) | 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA) |
| Package Code | BGA | β |
| Terminal Form | Ball | β |
| No. of Terminals | 672 | β |
| Package Shape | Square | β |
| Speed Grade | -2X | -2 |
| Operating Temperature | -40C to +85C (industrial) | Commercial (0 Β°C to +70 Β°C) [DATA_NEEDED: industrial variant] |
| Core Voltage | 1.8 V | 2.5 V |
| I/O Voltage Support | 1.8V / 2.5V / 3.3V / 5V (MultiVolt) | β |
| Configuration Method | SRAM (serial EPROM or JTAG) | β |
| JTAG Support | Yes (IEEE 1149.1) | β |
| Process Technology | 0.18 um CMOS, 6-metal | 0.22 Β΅m CMOS |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | Compliant (lead-free) |
| Logic Elements / Cells | β | 16,640 |
| Maximum User I/O | β | 488 |
| Embedded Memory Bits | β | 212,992 bits |
| Embedded Array Blocks (EABs) | β | [DATA_NEEDED: EAB count per family datasheet] |
| Maximum Frequency | β | 200 MHz |
| Package Body Size | β | 27 x 27 mm |
| Terminal Pitch | β | 1.0 mm |
| Propagation Delay | β | 3.1 ns |
| Moisture Sensitivity Level (MSL) | β | 3 |
| Peak Reflow Temperature | β | 220 Β°C |
| Mounting Type | β | Surface Mount |
| Configuration Modes | β | PS, PPS, PPA, JTAG |
| Supported I/O Standards | β | LVTTL, LVCMOS, SSTL, HSTL |