EP20K400FI672-2X vs EP20K400FI672-2N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400FI672-2X sa pamamagitan ng Intel at EP20K400FI672-2N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K400FI672-2X EP20K400FI672-2N
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND NRND
Family APEX 20K APEX 20K
Logic Elements 16,640 —
Typical Gates 400,000 system gates 400,000
Embedded Memory 212,992 bits —
User I/O Pins 496 —
Packhaging 672-ball BGA (FI672) 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA)
Package Code BGA —
Terminal Form Ball —
No. of Terminals 672 —
Package Shape Square —
Speed Grade -2X -2
Temperature na Operasyon -40C to +85C (industrial) Commercial (0 °C to +70 °C) [DATA_NEEDED: industrial variant]
Core Voltage 1.8 V 2.5 V
I/O Voltage Support 1.8V / 2.5V / 3.3V / 5V (MultiVolt) —
Configuration Method SRAM (serial EPROM or JTAG) —
JTAG Support Yes (IEEE 1149.1) —
Process Technology 0.18 um CMOS, 6-metal 0.22 µm CMOS
Tindminan RoHS [DATA_NEEDED: RoHS compliance] Compliant (lead-free)
Logic Elements / Cells — 16,640
Maximum User I/O — 488
Embedded Memory Bits — 212,992 bits
Embedded Array Blocks (EABs) — [DATA_NEEDED: EAB count per family datasheet]
Maximum Frequency — 200 MHz
Package Body Size — 27 x 27 mm
Terminal Pitch — 1.0 mm
Propagation Delay — 3.1 ns
Level ng Sensitivity sa Asid ng Moisture (MSL) — 3
Peak Reflow Temperature — 220 °C
Uri ng Pagpapasok — Surface Mount
Configuration Modes — PS, PPS, PPA, JTAG
Supported I/O Standards — LVTTL, LVCMOS, SSTL, HSTL

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