EP20K400GI655-3 vs EP20K400GI655-2 Comparison
Detailed side-by-side comparison of EP20K400GI655-3 by Altera and EP20K400GI655-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400GI655-3 | EP20K400GI655-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $55.00 | $175.00 |
| Family | APEX 20KE | β |
| Logic Elements / Cells | 16,640 | β |
| System Gates | 400,000 (maximum) | β |
| Maximum User I/O | 502 | 496 |
| Dedicated Inputs | 4 | 6 |
| Number of Terminals | 655 | 655 |
| Package | 655-Pin PGA (Plastic/CPGA, square) | SPGA-655 (47 mm x 47 mm) |
| JESD-30 Code | S-CPGA-P655 | β |
| Package Shape | Square | β |
| Form of Terminal | PIN/PEG (through-hole) | β |
| Mounting Type | Through-Hole (Socket) | Through-Hole / Socket |
| Process Technology | CMOS, 2.5V core | β |
| Core Supply Voltage | 2.5 V | β |
| I/O Supply Voltage | 2.5 V or 3.3 V (MultiVolt I/O) | β |
| Operating Temperature | 0Β°C to 70Β°C (Industrial I grade) | -40C to +85C (industrial) |
| Speed Grade | -3 (slowest of the EP20K400 family) | β |
| Configuration Modes | Passive Serial, Passive Parallel Asynchronous, JTAG | β |
| Embedded Memory | Dual-port RAM via Embedded System Blocks (ESBs) | Embedded System Blocks (ESBs) |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Manufacturer | β | Altera Corporation |
| Series | β | APEX 20K (EP20K400) |
| Device Type | β | Field Programmable Gate Array (FPGA) |
| Typical Gate Count | β | 400,000 gates |
| Logic Elements (LE) | β | 16,640 |
| Nominal Supply Voltage | β | 2.5 V |
| Supply Voltage Range | β | 2.375 V to 2.625 V |
| Propagation Delay | β | 3.1 ns (typical) |
| Technology | β | CMOS SRAM |
| Moisture Sensitivity Level | β | 1 (per Altera family) |
| Configuration Method | β | JTAG, Passive Serial, Passive Parallel |
| I/O Standards Supported | β | LVTTL, LVCMOS, PCI, GTL+ |
| Lifecycle Status | β | Obsolete (legacy Altera APEX 20K family) |