EP20K400GI655-3 vs EP20K400GI655-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GI655-3 sa pamamagitan ng Altera at EP20K400GI655-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400GI655-3 | EP20K400GI655-2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KE | — |
| Logic Elements / Cells | 16,640 | — |
| System Gates | 400,000 (maximum) | — |
| Maximum User I/O | 502 | 496 |
| Dedicated Inputs | 4 | 6 |
| Number of Terminals | 655 | 655 |
| Packhaging | 655-Pin PGA (Plastic/CPGA, square) | SPGA-655 (47 mm x 47 mm) |
| JESD-30 Code | S-CPGA-P655 | — |
| Package Shape | Square | — |
| Form of Terminal | PIN/PEG (through-hole) | — |
| Uri ng Pagpapasok | Through-Hole (Socket) | Through-Hole / Socket |
| Process Technology | CMOS, 2.5V core | — |
| Core Supply Voltage | 2.5 V | — |
| I/O Supply Voltage | 2.5 V or 3.3 V (MultiVolt I/O) | — |
| Temperature na Operasyon | 0°C to 70°C (Industrial I grade) | -40C to +85C (industrial) |
| Speed Grade | -3 (slowest of the EP20K400 family) | — |
| Configuration Modes | Passive Serial, Passive Parallel Asynchronous, JTAG | — |
| Embedded Memory | Dual-port RAM via Embedded System Blocks (ESBs) | Embedded System Blocks (ESBs) |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Manufacturer | — | Altera Corporation |
| Series | — | APEX 20K (EP20K400) |
| Device Type | — | Field Programmable Gate Array (FPGA) |
| Typical Gate Count | — | 400,000 gates |
| Logic Elements (LE) | — | 16,640 |
| Nominal Supply Voltage | — | 2.5 V |
| Supply Voltage Range | — | 2.375 V to 2.625 V |
| Propagation Delay | — | 3.1 ns (typical) |
| Technology | — | CMOS SRAM |
| Moisture Sensitivity Level | — | 1 (per Altera family) |
| Configuration Method | — | JTAG, Passive Serial, Passive Parallel |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, GTL+ |
| Katayuan ng Lifecycle | — | Obsolete (legacy Altera APEX 20K family) |