EP20K400GI655-3 vs EP20K400GI655-2 Comparación
Comparación detallada lado a lado de EP20K400GI655-3 por Altera y EP20K400GI655-2 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K400GI655-3 | EP20K400GI655-2 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $55,00 | $175,00 |
| Family | APEX 20KE | — |
| Logic Elements / Cells | 16,640 | — |
| System Gates | 400,000 (maximum) | — |
| Maximum User I/O | 502 | 496 |
| Dedicated Inputs | 4 | 6 |
| Number of Terminals | 655 | 655 |
| Encapsulado | 655-Pin PGA (Plastic/CPGA, square) | SPGA-655 (47 mm x 47 mm) |
| JESD-30 Code | S-CPGA-P655 | — |
| Package Shape | Square | — |
| Form of Terminal | PIN/PEG (through-hole) | — |
| Tipo de montaje | Through-Hole (Socket) | Through-Hole / Socket |
| Process Technology | CMOS, 2.5V core | — |
| Core Supply Voltage | 2.5 V | — |
| I/O Supply Voltage | 2.5 V or 3.3 V (MultiVolt I/O) | — |
| Temperatura de funcionamiento | 0°C to 70°C (Industrial I grade) | -40C to +85C (industrial) |
| Speed Grade | -3 (slowest of the EP20K400 family) | — |
| Configuration Modes | Passive Serial, Passive Parallel Asynchronous, JTAG | — |
| Embedded Memory | Dual-port RAM via Embedded System Blocks (ESBs) | Embedded System Blocks (ESBs) |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Manufacturer | — | Altera Corporation |
| Series | — | APEX 20K (EP20K400) |
| Device Type | — | Field Programmable Gate Array (FPGA) |
| Typical Gate Count | — | 400,000 gates |
| Logic Elements (LE) | — | 16,640 |
| Nominal Supply Voltage | — | 2.5 V |
| Supply Voltage Range | — | 2.375 V to 2.625 V |
| Propagation Delay | — | 3.1 ns (typical) |
| Technology | — | CMOS SRAM |
| Moisture Sensitivity Level | — | 1 (per Altera family) |
| Configuration Method | — | JTAG, Passive Serial, Passive Parallel |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, GTL+ |
| Estado del ciclo de vida | — | Obsolete (legacy Altera APEX 20K family) |