EP20K600CF33C8 vs EP20K600CF33C9 Comparison
Detailed side-by-side comparison of EP20K600CF33C8 by Altera and EP20K600CF33C9 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K600CF33C8 | EP20K600CF33C9 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $285.75 | $171.00 |
| Family | APEX 20KC | APEX 20KC |
| Device Type | FPGA (Field Programmable Gate Array) | β |
| Typical Gates | 600,000 | β |
| Logic Elements | 24,320 | β |
| Embedded RAM Bits | 311,296 | β |
| Embedded System Blocks (ESB) | 152 | β |
| Maximum User I/O | 488 | β |
| Process Technology | 0.15 Β΅m CMOS | 0.15 Β΅m CMOS |
| Core Voltage (VCCINT) | 1.8 V | β |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V (bank-selectable) | β |
| LVDS Support | Yes, up to 840 Mbps | β |
| PLLs | 4 enhanced PLLs | β |
| Package | 1020-ball FineLine BGA (FC-FBGA), 33 x 33 mm | 1020-ball FC-FBGA |
| Speed Grade | -8 | β |
| Operating Temperature | Commercial (0 Β°C to +85 Β°C) | β |
| Configuration Modes | Passive Serial, Passive Parallel Asynchronous, Passive Parallel Synchronous, JTAG | β |
| RoHS Status | Compliant (lead-free version) / non-compliant for legacy C-speed grade variant | [DATA_NEEDED: rohs status] |
| Status | NRND / Last-Time-Buy (per Altera/Intel product notice) | β |
| System Gates | β | 600,000 (maximum) |
| Logic Elements / Cells | β | 24,320 |
| Maximum Operating Frequency | β | 250 MHz |
| Maximum Clock Frequency | β | 303.03 MHz |
| Propagation Delay | β | 2.0 ns |
| Core Supply Voltage (VCCINT) | β | 1.8 V nominal (1.71 V to 1.89 V) |
| User I/O | β | 588 (4 dedicated inputs + 580 general-purpose I/O) |
| Mounting Type | β | Surface Mount (BGA) |
| Operating Temperature Range | β | [DATA_NEEDED: operating temperature range] |
| Embedded RAM | β | Dual-port RAM blocks (per family) |
| Programmability | β | JTAG / IEEE 1149.1 ISP, SRAM-based |
| MSL Level | β | [DATA_NEEDED: MSL level] |
| Logic Block Architecture | β | MultiCore (LUT + product-term + embedded memory) |
| I/O Standards Supported | β | LVTTL, LVCMOS, LVDS (per family datasheet) |