EP20K600CF33C8 vs EP20K600CF33C9 Comparaison
Comparaison détaillée côte à côte de EP20K600CF33C8 par Altera et EP20K600CF33C9 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K600CF33C8 | EP20K600CF33C9 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $285,75 | $171,00 |
| Family | APEX 20KC | APEX 20KC |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Typical Gates | 600,000 | — |
| Logic Elements | 24,320 | — |
| Embedded RAM Bits | 311,296 | — |
| Embedded System Blocks (ESB) | 152 | — |
| Maximum User I/O | 488 | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm CMOS |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V (bank-selectable) | — |
| LVDS Support | Yes, up to 840 Mbps | — |
| PLLs | 4 enhanced PLLs | — |
| Boîtier | 1020-ball FineLine BGA (FC-FBGA), 33 x 33 mm | 1020-ball FC-FBGA |
| Speed Grade | -8 | — |
| Température de fonctionnement | Commercial (0 °C to +85 °C) | — |
| Configuration Modes | Passive Serial, Passive Parallel Asynchronous, Passive Parallel Synchronous, JTAG | — |
| Statut RoHS | Compliant (lead-free version) / non-compliant for legacy C-speed grade variant | [DATA_NEEDED: rohs status] |
| Status | NRND / Last-Time-Buy (per Altera/Intel product notice) | — |
| System Gates | — | 600,000 (maximum) |
| Logic Elements / Cells | — | 24,320 |
| Maximum Operating Frequency | — | 250 MHz |
| Fréquence d'horloge maximale | — | 303.03 MHz |
| Propagation Delay | — | 2.0 ns |
| Core Supply Voltage (VCCINT) | — | 1.8 V nominal (1.71 V to 1.89 V) |
| User I/O | — | 588 (4 dedicated inputs + 580 general-purpose I/O) |
| Type de montage | — | Surface Mount (BGA) |
| Plage de température de fonctionnement | — | [DATA_NEEDED: operating temperature range] |
| Embedded RAM | — | Dual-port RAM blocks (per family) |
| Programmability | — | JTAG / IEEE 1149.1 ISP, SRAM-based |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |
| Logic Block Architecture | — | MultiCore (LUT + product-term + embedded memory) |
| I/O Standards Supported | — | LVTTL, LVCMOS, LVDS (per family datasheet) |