EP20K600CF33C8 vs EP20K600CF33C9 Comparación
Comparación detallada lado a lado de EP20K600CF33C8 por Altera y EP20K600CF33C9 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K600CF33C8 | EP20K600CF33C9 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $285,75 | $171,00 |
| Family | APEX 20KC | APEX 20KC |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Typical Gates | 600,000 | — |
| Logic Elements | 24,320 | — |
| Embedded RAM Bits | 311,296 | — |
| Embedded System Blocks (ESB) | 152 | — |
| Maximum User I/O | 488 | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm CMOS |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V (bank-selectable) | — |
| LVDS Support | Yes, up to 840 Mbps | — |
| PLLs | 4 enhanced PLLs | — |
| Encapsulado | 1020-ball FineLine BGA (FC-FBGA), 33 x 33 mm | 1020-ball FC-FBGA |
| Speed Grade | -8 | — |
| Temperatura de funcionamiento | Commercial (0 °C to +85 °C) | — |
| Configuration Modes | Passive Serial, Passive Parallel Asynchronous, Passive Parallel Synchronous, JTAG | — |
| Estado RoHS | Compliant (lead-free version) / non-compliant for legacy C-speed grade variant | [DATA_NEEDED: rohs status] |
| Status | NRND / Last-Time-Buy (per Altera/Intel product notice) | — |
| System Gates | — | 600,000 (maximum) |
| Logic Elements / Cells | — | 24,320 |
| Maximum Operating Frequency | — | 250 MHz |
| Frecuencia de reloj máxima | — | 303.03 MHz |
| Propagation Delay | — | 2.0 ns |
| Core Supply Voltage (VCCINT) | — | 1.8 V nominal (1.71 V to 1.89 V) |
| User I/O | — | 588 (4 dedicated inputs + 580 general-purpose I/O) |
| Tipo de montaje | — | Surface Mount (BGA) |
| Rango de temperatura de funcionamiento | — | [DATA_NEEDED: operating temperature range] |
| Embedded RAM | — | Dual-port RAM blocks (per family) |
| Programmability | — | JTAG / IEEE 1149.1 ISP, SRAM-based |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |
| Logic Block Architecture | — | MultiCore (LUT + product-term + embedded memory) |
| I/O Standards Supported | — | LVTTL, LVCMOS, LVDS (per family datasheet) |