EP20K60EFC144-2XN vs EP20K60EFI144-2X Comparison
Detailed side-by-side comparison of EP20K60EFC144-2XN by Altera and EP20K60EFI144-2X by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K60EFC144-2XN - APEX-20KE FPGA 60K Gates 93 I/O 144-BGA | Intel/Altera
EP20K60EFC144-2XN NrndSpecification Comparison
| Parameter | EP20K60EFC144-2XN | EP20K60EFI144-2X |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $152.00 | $65.00 |
| Series | APEX-20KE | β |
| Family | APEX-20K (MultiCore Architecture) | β |
| Typical Gate Count | 60,000 gates | β |
| Logic Elements / Embedded Array Blocks | 2,560 | β |
| Embedded Memory (Bits) | 32,768 | β |
| Maximum User I/O | 93 | β |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | β |
| Core Supply Voltage (VCCINT) | 1.71 V to 1.89 V | 1.8 V (range 1.71 V to 1.89 V) |
| I/O Supply Voltage (VCCIO) | [DATA_NEEDED: VCCIO range] | β |
| Package Type | 144-BGA (Fine-pitch Ball Grid Array) | FBGA-144 (FineLine BGA, LBGA) |
| Package Code (per MPN suffix) | FBGA / LBGA, 13x13 mm | β |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature (TJ) | 0 C to +85 C (commercial) | β |
| Speed Grade | -2 (per MPN suffix) | -2 (industrial, -2X suffix) |
| Configuration Method | JTAG (IEEE 1149.1), Passive Serial, Parallel | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Logic Family | CMOS, SRAM-based LUT | β |
| Device Family | β | APEX 20KE |
| Typical Gates | β | 60,000 |
| Logic Elements | β | 2,560 |
| Maximum Operating Frequency | β | 200 MHz |
| Process Technology | β | 0.22 Β΅m CMOS |
| Propagation Delay (tpd) | β | 2.41 ns |
| User I/O Pins | β | 93 |
| Dedicated Inputs | β | 4 |
| Total Terminals | β | 144 |
| Package Code | β | LBGA |
| Terminal Form | β | Ball |
| Architecture | β | MultiCore (LUT + product-term + embedded memory) |
| I/O Standard Support | β | LVDS, 1.8 V I/O |
| Operating Temperature | β | -40 Β°C to +85 Β°C |
| Configuration Interface | β | JTAG (IEEE 1149.1) / serial PROM / parallel PROM |
| Moisture Sensitivity Level (MSL) | β | 3 |