EP20K60EFC144-2XN vs EP20K60EFI144-2X 对比

详细并排对比 EP20K60EFC144-2XN 出自 Altera 和 EP20K60EFI144-2X 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K60EFC144-2XN EP20K60EFI144-2X
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $152.00 $65.00
Series APEX-20KE —
Family APEX-20K (MultiCore Architecture) —
Typical Gate Count 60,000 gates —
Logic Elements / Embedded Array Blocks 2,560 —
Embedded Memory (Bits) 32,768 —
Maximum User I/O 93 —
Number of I/O Banks [DATA_NEEDED: number of I/O banks] —
Core Supply Voltage (VCCINT) 1.71 V to 1.89 V 1.8 V (range 1.71 V to 1.89 V)
I/O Supply Voltage (VCCIO) [DATA_NEEDED: VCCIO range] —
Package Type 144-BGA (Fine-pitch Ball Grid Array) FBGA-144 (FineLine BGA, LBGA)
Package Code (per MPN suffix) FBGA / LBGA, 13x13 mm —
安装类型 Surface Mount Surface Mount
Operating Temperature (TJ) 0 C to +85 C (commercial) —
Speed Grade -2 (per MPN suffix) -2 (industrial, -2X suffix)
Configuration Method JTAG (IEEE 1149.1), Passive Serial, Parallel —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Logic Family CMOS, SRAM-based LUT —
Device Family — APEX 20KE
Typical Gates — 60,000
Logic Elements — 2,560
Maximum Operating Frequency — 200 MHz
Process Technology — 0.22 µm CMOS
Propagation Delay (tpd) — 2.41 ns
User I/O Pins — 93
Dedicated Inputs — 4
Total Terminals — 144
Package Code — LBGA
Terminal Form — Ball
Architecture — MultiCore (LUT + product-term + embedded memory)
I/O Standard Support — LVDS, 1.8 V I/O
工作温度 — -40 °C to +85 °C
Configuration Interface — JTAG (IEEE 1149.1) / serial PROM / parallel PROM
湿敏等级(MSL) — 3

数据手册与资源

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