EP2S130F1020I4N vs EP2S130F1020C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2S130F1020I4N sa pamamagitan ng Intel at EP2S130F1020C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP2S130F1020I4N - Stratix II 132K LEs FPGA, 742 I/O | Intel / Altera
EP2S130F1020I4N ✗ Tapus ng Buhay
Pagsanggunian na paghahambing
| Parametro | EP2S130F1020I4N | EP2S130F1020C5N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Tapus ng Buhay | NRND |
| Family | Stratix II | Stratix II |
| Logic Elements | 132,540 | 132,540 |
| Logic Array Blocks (LABs) | 6,627 | — |
| Total RAM Bits | 6,747,840 | — |
| User I/O Count | 742 | — |
| Core Voltage (VCCINT) | 1.15 V to 1.25 V | — |
| Temperature na Operasyon | -40C to +100C (TJ, Industrial) | Commercial (0C to +85C, C5 grade) |
| Packhaging / Kaso | 1020-BBGA (FineLine BGA, FC-FBGA) | — |
| Supplier Device Package | 1020-FBGA | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Process Node | 90 nm | — |
| Internal Operating Frequency | up to 711.24 MHz | — |
| Speed Grade | I4 (Industrial, speed bin 4) | — |
| Configuration | SRAM-based, volatile configuration memory | — |
| Design Software | Quartus II (legacy) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs status] |
| Lead-Free | [DATA_NEEDED: lead-free / lead-bearing finish] | [DATA_NEEDED: lead-free status] |
| Adaptive Logic Modules (ALMs) | — | 6627 LABs (per Jotrin listing) |
| Total Memory Bits | — | 6,747,840 bits |
| User I/Os | — | 734 |
| Process Technology | — | 90 nm |
| Core Supply Voltage (VCCINT) | — | 1.15 V to 1.25 V |
| Maximum Internal Frequency | — | 609.76 MHz |
| Packhaging | — | 1020-ball FC-FBGA (33x33 mm) |
| Temperature Grade | — | C5 (other - per Partstack) |
| PLLs | — | 4 (typical Stratix II feature) |
| Global Clock Networks | — | 16 (typical Stratix II feature) |
| Configuration Method | — | Serial/Parallel via Quartus II (typical Stratix II) |
| Country of Origin | — | Republic of Korea (per GlobalSpec) |
| ECCN | — | 3A001.a.7.a (per GlobalSpec) |
| Estimated EOL Date | — | 2023 (per GlobalSpec) |