EP610DC-10 vs EP610DC-20 Comparison
Detailed side-by-side comparison of EP610DC-10 by Intel and EP610DC-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-10 | EP610DC-20 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 16 | — |
| Maximum Pipelined Data Rate | 100 MHz | — |
| Pin-to-Pin Propagation Delay (tpd) | 10 ns | — |
| Speed Grade | -10 | — |
| Package | 24-pin CDIP (Ceramic DIP, windowed) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Mounting Type | Through-Hole | Through-hole |
| Technology | CMOS, EPROM-based (UV-erasable) | — |
| Supply Voltage | 5 V (single supply) | — |
| Operating Temperature | 0C to +70C (commercial) | 0 °C to 70 °C (commercial) |
| I/O Pins | [DATA_NEEDED: exact I/O count for CDIP-24 variant] | 16 (bidirectional) |
| Logic Elements | 16 macrocells (programmable AND/OR array) | — |
| Configuration Memory | UV-erasable EPROM | — |
| Reprogrammable | Yes (UV erase window on package) | — |
| RoHS Status | [DATA_NEEDED: not stated in verified web data] | [DATA_NEEDED: RoHS compliance status] |
| Product Type | — | CMOS UV-Erasable Programmable Logic Device (EPLD) |
| Family | — | Classic EP610 |
| Logic Macrocells | — | 16 |
| Dedicated Inputs | — | 4 |
| Total Usable Pins | — | 20 |
| Product Terms (p-terms) | — | 160 |
| Propagation Delay (tPD) | — | 22 ns |
| Maximum Toggle Frequency (fMAX) | — | 55.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Programming Method | — | UV erasure + parallel programmer |
| Process Technology | — | CMOS, UV-erasable floating gate |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |