EP610DC-10 vs EP610DC-20 比較
詳細並排比較 EP610DC-10 由 Intel 與 EP610DC-20 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610DC-10 | EP610DC-20 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 16 | — |
| Maximum Pipelined Data Rate | 100 MHz | — |
| Pin-to-Pin Propagation Delay (tpd) | 10 ns | — |
| Speed Grade | -10 | — |
| 封裝 | 24-pin CDIP (Ceramic DIP, windowed) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| 安裝類型 | Through-Hole | Through-hole |
| Technology | CMOS, EPROM-based (UV-erasable) | — |
| 供應電壓 | 5 V (single supply) | — |
| 工作溫度 | 0C to +70C (commercial) | 0 °C to 70 °C (commercial) |
| I/O Pins | [DATA_NEEDED: exact I/O count for CDIP-24 variant] | 16 (bidirectional) |
| Logic Elements | 16 macrocells (programmable AND/OR array) | — |
| Configuration Memory | UV-erasable EPROM | — |
| Reprogrammable | Yes (UV erase window on package) | — |
| RoHS 狀態 | [DATA_NEEDED: not stated in verified web data] | [DATA_NEEDED: RoHS compliance status] |
| Product Type | — | CMOS UV-Erasable Programmable Logic Device (EPLD) |
| Family | — | Classic EP610 |
| Logic Macrocells | — | 16 |
| Dedicated Inputs | — | 4 |
| Total Usable Pins | — | 20 |
| Product Terms (p-terms) | — | 160 |
| Propagation Delay (tPD) | — | 22 ns |
| Maximum Toggle Frequency (fMAX) | — | 55.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Programming Method | — | UV erasure + parallel programmer |
| Process Technology | — | CMOS, UV-erasable floating gate |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |