EP610DC-10 vs EP610DI-25 Comparison
Detailed side-by-side comparison of EP610DC-10 by Intel and EP610DI-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP610DC-10
EP610DC-10 - 16-Macrocell Classic EPLD, 10ns, 24-Pin CDIP | Intel
EP610DC-10 ObsoleteSpecification Comparison
| Parameter | EP610DC-10 | EP610DI-25 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.95 | $9.95 |
| Device Family | Altera Classic EPLD | β |
| Macrocells | 16 | 16 |
| Maximum Pipelined Data Rate | 100 MHz | β |
| Pin-to-Pin Propagation Delay (tpd) | 10 ns | β |
| Speed Grade | -10 | β |
| Package | 24-pin CDIP (Ceramic DIP, windowed) | β |
| Mounting Type | Through-Hole | Through-Hole (DIP) |
| Technology | CMOS, EPROM-based (UV-erasable) | CMOS EPROM (UV-erasable) |
| Supply Voltage | 5 V (single supply) | β |
| Operating Temperature | 0C to +70C (commercial) | Industrial (per "I" suffix) |
| I/O Pins | [DATA_NEEDED: exact I/O count for CDIP-24 variant] | 16 (bidirectional) |
| Logic Elements | 16 macrocells (programmable AND/OR array) | β |
| Configuration Memory | UV-erasable EPROM | β |
| Reprogrammable | Yes (UV erase window on package) | β |
| RoHS Status | [DATA_NEEDED: not stated in verified web data] | β |
| Part Family | β | Classic EPLD |
| Propagation Delay (tPD) | β | 25 ns |
| Maximum Pipelined Clock Frequency | β | 100 MHz (max fCNT, per family datasheet) |
| Dedicated Inputs | β | 4 |
| Total User I/O | β | 20 |
| Supply Voltage (VCC) | β | 5 V nominal |
| Package Type | β | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 |
| Pin Count | β | 24 |
| Speed Grade Suffix | β | 25 = 25 ns |
| Compliance | β | RoHS status unknown (legacy 1990s part) |