EP610DC-10 vs EP610IDC-10 Comparison
Detailed side-by-side comparison of EP610DC-10 by Intel and EP610IDC-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-10 | EP610IDC-10 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.95 | $8.85 |
| Device Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 16 | β |
| Maximum Pipelined Data Rate | 100 MHz | β |
| Pin-to-Pin Propagation Delay (tpd) | 10 ns | β |
| Speed Grade | -10 | β |
| Package | 24-pin CDIP (Ceramic DIP, windowed) | β |
| Mounting Type | Through-Hole | Through-hole |
| Technology | CMOS, EPROM-based (UV-erasable) | CMOS, UV-erasable (windowed ceramic) |
| Supply Voltage | 5 V (single supply) | β |
| Operating Temperature | 0C to +70C (commercial) | β |
| I/O Pins | [DATA_NEEDED: exact I/O count for CDIP-24 variant] | 20 |
| Logic Elements | 16 macrocells (programmable AND/OR array) | β |
| Configuration Memory | UV-erasable EPROM | β |
| Reprogrammable | Yes (UV erase window on package) | β |
| RoHS Status | [DATA_NEEDED: not stated in verified web data] | [DATA_NEEDED: RoHS status of CDIP-10 variant] |
| Logic Capacity | β | 300 usable gates |
| Macrocell Count | β | 16 macrocells |
| Pin-to-Pin Logic Delay (tpd) | β | 10 ns |
| Maximum Counter Frequency (fCNT) | β | 100 MHz |
| Supply Voltage (VCC) | β | 5 V (nominal) |
| I/O Logic Compatibility | β | 100% TTL emulation |
| Package Type | β | 24-pin Ceramic DIP (CDIP) |
| Dedicated Inputs | β | 4 |
| Operating Temperature Range | β | 0 Β°C to +70 Β°C (commercial) |
| Programmable Interconnect | β | Yes (on-chip) |
| In-System Programmability | β | Yes (via MAX+PLUS II) |
| Boundary-Scan Test | β | Yes (per device documentation) |