EP610DC-10 vs EP610IDC-10 Comparison
Detailed side-by-side comparison of EP610DC-10 by Intel and EP610IDC-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-10 | EP610IDC-10 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 16 | — |
| Maximum Pipelined Data Rate | 100 MHz | — |
| Pin-to-Pin Propagation Delay (tpd) | 10 ns | — |
| Speed Grade | -10 | — |
| Package | 24-pin CDIP (Ceramic DIP, windowed) | — |
| Mounting Type | Through-Hole | Through-hole |
| Technology | CMOS, EPROM-based (UV-erasable) | CMOS, UV-erasable (windowed ceramic) |
| Supply Voltage | 5 V (single supply) | — |
| Operating Temperature | 0C to +70C (commercial) | — |
| I/O Pins | [DATA_NEEDED: exact I/O count for CDIP-24 variant] | 20 |
| Logic Elements | 16 macrocells (programmable AND/OR array) | — |
| Configuration Memory | UV-erasable EPROM | — |
| Reprogrammable | Yes (UV erase window on package) | — |
| RoHS Status | [DATA_NEEDED: not stated in verified web data] | [DATA_NEEDED: RoHS status of CDIP-10 variant] |
| Logic Capacity | — | 300 usable gates |
| Macrocell Count | — | 16 macrocells |
| Pin-to-Pin Logic Delay (tpd) | — | 10 ns |
| Maximum Counter Frequency (fCNT) | — | 100 MHz |
| Supply Voltage (VCC) | — | 5 V (nominal) |
| I/O Logic Compatibility | — | 100% TTL emulation |
| Package Type | — | 24-pin Ceramic DIP (CDIP) |
| Dedicated Inputs | — | 4 |
| Operating Temperature Range | — | 0 °C to +70 °C (commercial) |
| Programmable Interconnect | — | Yes (on-chip) |
| In-System Programmability | — | Yes (via MAX+PLUS II) |
| Boundary-Scan Test | — | Yes (per device documentation) |