EP610DC-25 vs EP610DI-30N Comparison
Detailed side-by-side comparison of EP610DC-25 by Rochester Electronics and EP610DI-30N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ ActiveSpecification Comparison
| Parameter | EP610DC-25 | EP610DI-30N |
|---|---|---|
| Brand | Rochester Electronics | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EP610 |
| Product Type | EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 16 | 16 |
| Equivalent Gates | 300 | — |
| Maximum Propagation Delay (tPD) | 25 ns | — |
| Pipelined Data Rate | Up to 100 MHz | — |
| Number of I/O Pins | 22 | — |
| Number of Dedicated Inputs | 4 | — |
| Total Pin Count | 24 | — |
| Package | 24-pin CDIP (Ceramic DIP, through-hole) | CDIP-24 (Ceramic DIP, windowed) |
| Mounting Type | Through Hole | Through-hole (DIP) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V ±5% |
| Operating Temperature | 0 C to +70 C | -40°C to +85°C (industrial) |
| Technology | CMOS EPROM (UV-erasable) | — |
| Programming Method | JEDEC fuse-map / UV-erase | UV-erasable (windowed ceramic) |
| Speed Grade Suffix | -25 (25 ns tPD) | — |
| Usable Gates | — | 300 |
| Propagation Delay (tPD) | — | 30 ns |
| Maximum Frequency | — | 33.3 MHz (system); 100 MHz (pipelined) |
| Pin Count | — | 24 |
| Process Technology | — | CMOS |
| MSL Level | — | [DATA_NEEDED: MSL level] |
| RoHS Status | — | [DATA_NEEDED: RoHS status] |