EP610DC-25 vs EP610DI-30N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP610DC-25 disebabkan oleh Rochester Electronics dan EP610DI-30N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ AktifPengandingan Spesifikasi
| Parametr | EP610DC-25 | EP610DI-30N |
|---|---|---|
| Merek | Rochester Electronics | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Aktif | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EP610 |
| Product Type | EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 16 | 16 |
| Equivalent Gates | 300 | — |
| Maximum Propagation Delay (tPD) | 25 ns | — |
| Pipelined Data Rate | Up to 100 MHz | — |
| Number of I/O Pins | 22 | — |
| Number of Dedicated Inputs | 4 | — |
| Total Pin Count | 24 | — |
| Kemasan | 24-pin CDIP (Ceramic DIP, through-hole) | CDIP-24 (Ceramic DIP, windowed) |
| Jenis Pemasangan | Through Hole | Through-hole (DIP) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V ±5% |
| Suhu Operasi | 0 C to +70 C | -40°C to +85°C (industrial) |
| Technology | CMOS EPROM (UV-erasable) | — |
| Programming Method | JEDEC fuse-map / UV-erase | UV-erasable (windowed ceramic) |
| Speed Grade Suffix | -25 (25 ns tPD) | — |
| Usable Gates | — | 300 |
| Propagation Delay (tPD) | — | 30 ns |
| Maximum Frequency | — | 33.3 MHz (system); 100 MHz (pipelined) |
| Kiraan Pin | — | 24 |
| Process Technology | — | CMOS |
| Aras MSL | — | [DATA_NEEDED: MSL level] |
| Status RoHS | — | [DATA_NEEDED: RoHS status] |