EP610DC-30 vs EP610DI-30N Comparison
Detailed side-by-side comparison of EP610DC-30 by Altera and EP610DI-30N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-30 | EP610DI-30N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Family | EP610 (Classic Device Family) | Altera Classic EP610 |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 (4 product terms per macrocell) | — |
| Usable Gates | 300 | 300 |
| Maximum Pipelined Clock Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 30 ns | 30 ns |
| Dedicated Inputs | 16 | — |
| I/O Pins | 16 (with output enable) | — |
| Package | 24-pin CERDIP (windowed) | CDIP-24 (Ceramic DIP, windowed) |
| Mounting Type | Through-Hole | Through-hole (DIP) |
| Speed Grade | -30 (30 ns tPD) | — |
| Technology | CMOS EPROM | — |
| Programmability | UV-erasable, windowed EPROM | — |
| Security Bit | Yes (protects design after programming) | — |
| Output Modes | Registered and Combinatorial | — |
| Operating Temperature | Commercial (0C to +70C) | -40°C to +85°C (industrial) |
| Maximum Frequency | — | 33.3 MHz (system); 100 MHz (pipelined) |
| Supply Voltage (VCC) | — | 5 V ±5% |
| Pin Count | — | 24 |
| Process Technology | — | CMOS |
| Programming Method | — | UV-erasable (windowed ceramic) |
| MSL Level | — | [DATA_NEEDED: MSL level] |
| RoHS Status | — | [DATA_NEEDED: RoHS status] |