EP610DC-30 vs EP610DI-30N 비교
다음의 상세 나란히 비교: EP610DC-30 제조: Altera 및 EP610DI-30N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP610DC-30 | EP610DI-30N |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | NRND | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $10.40 | $17.80 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Family | EP610 (Classic Device Family) | Altera Classic EP610 |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 (4 product terms per macrocell) | — |
| Usable Gates | 300 | 300 |
| Maximum Pipelined Clock Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 30 ns | 30 ns |
| Dedicated Inputs | 16 | — |
| I/O Pins | 16 (with output enable) | — |
| 패키지 | 24-pin CERDIP (windowed) | CDIP-24 (Ceramic DIP, windowed) |
| 실장 유형 | Through-Hole | Through-hole (DIP) |
| Speed Grade | -30 (30 ns tPD) | — |
| Technology | CMOS EPROM | — |
| Programmability | UV-erasable, windowed EPROM | — |
| Security Bit | Yes (protects design after programming) | — |
| Output Modes | Registered and Combinatorial | — |
| 동작 온도 | Commercial (0C to +70C) | -40°C to +85°C (industrial) |
| Maximum Frequency | — | 33.3 MHz (system); 100 MHz (pipelined) |
| Supply Voltage (VCC) | — | 5 V ±5% |
| 핀 수 | — | 24 |
| Process Technology | — | CMOS |
| Programming Method | — | UV-erasable (windowed ceramic) |
| MSL 레벨 | — | [DATA_NEEDED: MSL level] |
| RoHS 상태 | — | [DATA_NEEDED: RoHS status] |