EP610DC-30 vs EP610DI-30N Comparación
Comparación detallada lado a lado de EP610DC-30 por Altera y EP610DI-30N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP610DC-30 | EP610DI-30N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,40 | $17,80 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Family | EP610 (Classic Device Family) | Altera Classic EP610 |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 (4 product terms per macrocell) | — |
| Usable Gates | 300 | 300 |
| Maximum Pipelined Clock Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 30 ns | 30 ns |
| Dedicated Inputs | 16 | — |
| I/O Pins | 16 (with output enable) | — |
| Encapsulado | 24-pin CERDIP (windowed) | CDIP-24 (Ceramic DIP, windowed) |
| Tipo de montaje | Through-Hole | Through-hole (DIP) |
| Speed Grade | -30 (30 ns tPD) | — |
| Technology | CMOS EPROM | — |
| Programmability | UV-erasable, windowed EPROM | — |
| Security Bit | Yes (protects design after programming) | — |
| Output Modes | Registered and Combinatorial | — |
| Temperatura de funcionamiento | Commercial (0C to +70C) | -40°C to +85°C (industrial) |
| Maximum Frequency | — | 33.3 MHz (system); 100 MHz (pipelined) |
| Supply Voltage (VCC) | — | 5 V ±5% |
| Recuento de pines | — | 24 |
| Process Technology | — | CMOS |
| Programming Method | — | UV-erasable (windowed ceramic) |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |
| Estado RoHS | — | [DATA_NEEDED: RoHS status] |