EP610DC-30 vs EP610DI-30N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DC-30 sa pamamagitan ng Altera at EP610DI-30N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610DC-30 | EP610DI-30N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Family | EP610 (Classic Device Family) | Altera Classic EP610 |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 (4 product terms per macrocell) | — |
| Usable Gates | 300 | 300 |
| Maximum Pipelined Clock Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 30 ns | 30 ns |
| Dedicated Inputs | 16 | — |
| I/O Pins | 16 (with output enable) | — |
| Packhaging | 24-pin CERDIP (windowed) | CDIP-24 (Ceramic DIP, windowed) |
| Uri ng Pagpapasok | Through-Hole | Through-hole (DIP) |
| Speed Grade | -30 (30 ns tPD) | — |
| Technology | CMOS EPROM | — |
| Programmability | UV-erasable, windowed EPROM | — |
| Security Bit | Yes (protects design after programming) | — |
| Output Modes | Registered and Combinatorial | — |
| Temperature na Operasyon | Commercial (0C to +70C) | -40°C to +85°C (industrial) |
| Maximum Frequency | — | 33.3 MHz (system); 100 MHz (pipelined) |
| Supply Voltage (VCC) | — | 5 V ±5% |
| Bilang ng Pin | — | 24 |
| Process Technology | — | CMOS |
| Programming Method | — | UV-erasable (windowed ceramic) |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |