EP610DI-30 vs EP610IDC-15 Comparison
Detailed side-by-side comparison of EP610DI-30 by Rochester Electronics and EP610IDC-15 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP610DI-30
EP610DI-30 - 16-Macrocell Classic EPLD, 30ns, CERDIP-24 | Rochester Electronics
EP610DI-30 β ActiveIntel
EP610IDC-15
EP610IDC-15 - 16-Macrocell Classic EPLD, 15ns, 24-CerDIP | Intel
EP610IDC-15 β Last Time BuySpecification Comparison
| Parameter | EP610DI-30 | EP610IDC-15 |
|---|---|---|
| Brand | Rochester Electronics | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $23.50 | $9.95 |
| Device Type | EPLD (Erasable Programmable Logic Device) | β |
| Family | Classic EP610 | β |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 30 ns | 15 ns |
| Pipelined Data Rate | 100 MHz | β |
| Technology | CMOS | β |
| Supply Voltage | 5 V (single supply) | β |
| Package | CERDIP-24 (windowed, UV-erasable) | 24-pin CerDIP (ceramic DIP) |
| Mounting Type | Through-Hole | Through-hole |
| Programmable Elements | EPROM (UV-erasable, windowed) | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| I/O Pins | [DATA_NEEDED: I/O pin count] | 24 (per package; macrocell-programmable) |
| Logic Capacity | [DATA_NEEDED: usable gates / logic capacity] | β |
| RoHS Status | unknown | [DATA_NEEDED: RoHS status of CerDIP variant] |
| Lead-Free | unknown | β |
| Original Manufacturer | Altera (now Intel) | β |
| Current Supplier | Rochester Electronics (authorized continuing source) | β |
| MSL Level | N/A (through-hole, non-surface-mount) | β |
| Device Family | β | Altera Classic EPLD |
| Usable Gates | β | 300 |
| Maximum Frequency | β | 66 MHz |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V (5 V nominal) |
| Process Technology | β | CMOS, UV-erasable / OTP |
| Logic-Block Architecture | β | AND/OR macrocell array with programmable flip-flops |
| Program/Erase | β | UV-erasable, OTP-compatible |
| Development Tool | β | MAX+PLUS II |
| Programming Current | β | 11.0 mA typical (per Classic family datasheet) |