EP610DI-30 vs EP610IDC-15 比較
詳細並排比較 EP610DI-30 由 Rochester Electronics 與 EP610IDC-15 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP610DI-30 - 16-Macrocell Classic EPLD, 30ns, CERDIP-24 | Rochester Electronics
EP610DI-30 ✓ 啟用中規格比較
| 參數 | EP610DI-30 | EP610IDC-15 |
|---|---|---|
| 品牌 | Rochester Electronics | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 最後購買 |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic EP610 | — |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 30 ns | 15 ns |
| Pipelined Data Rate | 100 MHz | — |
| Technology | CMOS | — |
| 供應電壓 | 5 V (single supply) | — |
| 封裝 | CERDIP-24 (windowed, UV-erasable) | 24-pin CerDIP (ceramic DIP) |
| 安裝類型 | Through-Hole | Through-hole |
| Programmable Elements | EPROM (UV-erasable, windowed) | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| I/O Pins | [DATA_NEEDED: I/O pin count] | 24 (per package; macrocell-programmable) |
| Logic Capacity | [DATA_NEEDED: usable gates / logic capacity] | — |
| RoHS 狀態 | unknown | [DATA_NEEDED: RoHS status of CerDIP variant] |
| Lead-Free | unknown | — |
| Original Manufacturer | Altera (now Intel) | — |
| Current Supplier | Rochester Electronics (authorized continuing source) | — |
| MSL 等級 | N/A (through-hole, non-surface-mount) | — |
| Device Family | — | Altera Classic EPLD |
| Usable Gates | — | 300 |
| Maximum Frequency | — | 66 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Process Technology | — | CMOS, UV-erasable / OTP |
| Logic-Block Architecture | — | AND/OR macrocell array with programmable flip-flops |
| Program/Erase | — | UV-erasable, OTP-compatible |
| Development Tool | — | MAX+PLUS II |
| Programming Current | — | 11.0 mA typical (per Classic family datasheet) |