EP610DI-30 vs EP610IDC-15 Comparaison
Comparaison détaillée côte à côte de EP610DI-30 par Rochester Electronics et EP610IDC-15 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Rochester Electronics
EP610DI-30 - 16-Macrocell Classic EPLD, 30ns, CERDIP-24 | Rochester Electronics
EP610DI-30 ✓ ActifComparaison des spécifications
| Paramètre | EP610DI-30 | EP610IDC-15 |
|---|---|---|
| Marque | Rochester Electronics | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $23,50 | $9,95 |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic EP610 | — |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 30 ns | 15 ns |
| Pipelined Data Rate | 100 MHz | — |
| Technology | CMOS | — |
| Tension d'alimentation | 5 V (single supply) | — |
| Boîtier | CERDIP-24 (windowed, UV-erasable) | 24-pin CerDIP (ceramic DIP) |
| Type de montage | Through-Hole | Through-hole |
| Programmable Elements | EPROM (UV-erasable, windowed) | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| I/O Pins | [DATA_NEEDED: I/O pin count] | 24 (per package; macrocell-programmable) |
| Logic Capacity | [DATA_NEEDED: usable gates / logic capacity] | — |
| Statut RoHS | unknown | [DATA_NEEDED: RoHS status of CerDIP variant] |
| Lead-Free | unknown | — |
| Original Manufacturer | Altera (now Intel) | — |
| Current Supplier | Rochester Electronics (authorized continuing source) | — |
| Niveau MSL | N/A (through-hole, non-surface-mount) | — |
| Device Family | — | Altera Classic EPLD |
| Usable Gates | — | 300 |
| Maximum Frequency | — | 66 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Process Technology | — | CMOS, UV-erasable / OTP |
| Logic-Block Architecture | — | AND/OR macrocell array with programmable flip-flops |
| Program/Erase | — | UV-erasable, OTP-compatible |
| Development Tool | — | MAX+PLUS II |
| Programming Current | — | 11.0 mA typical (per Classic family datasheet) |