EP610DI-30 vs EP610IDC-15 Vergleich
Detaillierter Direktvergleich von EP610DI-30 von Rochester Electronics und EP610IDC-15 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Rochester Electronics
EP610DI-30 - 16-Macrocell Classic EPLD, 30ns, CERDIP-24 | Rochester Electronics
EP610DI-30 ✓ AktivIntel
EP610IDC-15 - 16-Macrocell Classic EPLD, 15ns, 24-CerDIP | Intel
EP610IDC-15 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP610DI-30 | EP610IDC-15 |
|---|---|---|
| Marke | Rochester Electronics | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $23,50 | $9,95 |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic EP610 | — |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 30 ns | 15 ns |
| Pipelined Data Rate | 100 MHz | — |
| Technology | CMOS | — |
| Versorgungsspannung | 5 V (single supply) | — |
| Gehäuse | CERDIP-24 (windowed, UV-erasable) | 24-pin CerDIP (ceramic DIP) |
| Montageart | Through-Hole | Through-hole |
| Programmable Elements | EPROM (UV-erasable, windowed) | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| I/O Pins | [DATA_NEEDED: I/O pin count] | 24 (per package; macrocell-programmable) |
| Logic Capacity | [DATA_NEEDED: usable gates / logic capacity] | — |
| RoHS-Status | unknown | [DATA_NEEDED: RoHS status of CerDIP variant] |
| Lead-Free | unknown | — |
| Original Manufacturer | Altera (now Intel) | — |
| Current Supplier | Rochester Electronics (authorized continuing source) | — |
| MSL-Level | N/A (through-hole, non-surface-mount) | — |
| Device Family | — | Altera Classic EPLD |
| Usable Gates | — | 300 |
| Maximum Frequency | — | 66 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Process Technology | — | CMOS, UV-erasable / OTP |
| Logic-Block Architecture | — | AND/OR macrocell array with programmable flip-flops |
| Program/Erase | — | UV-erasable, OTP-compatible |
| Development Tool | — | MAX+PLUS II |
| Programming Current | — | 11.0 mA typical (per Classic family datasheet) |