EP610DM-35 vs EP610IPC-10 Comparison
Detailed side-by-side comparison of EP610DM-35 by Altera and EP610IPC-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DM-35 | EP610IPC-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $23.40 | $16.40 |
| Manufacturer | Altera (Rochester Electronics authorized stock) | β |
| Part Family | Classic EPLD | β |
| Logic Family | PAL-type EPLD, CMOS, UV-erasable | β |
| Number of Macrocells | 16 | β |
| Number of Gates | 300 | β |
| Propagation Delay (tPD) | 35 ns | 15 ns (commerical -10 grade) |
| Pipelined Data Rate (fMAX) | 100 MHz | β |
| Supply Voltage (VCC) | 5 V (single supply) | β |
| Package | 24-pin CDIP (CERDIP) with UV window | 24-pin PDIP (Plastic DIP) |
| Temperature Grade (M) | Military -55Β°C to +125Β°C | β |
| I/O Pins | 24 dedicated I/O (input + bidirectional) | 16 |
| Programmability | UV-erasable, reprogrammable | β |
| Operating Temperature Range | -55Β°C to +125Β°C | β |
| MSL Level | [DATA_NEEDED: MSL rating] | β |
| RoHS Status | Non-compliant (contains lead, hermetic CERDIP) | β |
| Family | β | Altera Classic EPLD |
| Device Type | β | EPLD (Erasable Programmable Logic Device) |
| Programmable Gates | β | 300 usable gates |
| Macrocells | β | 16 |
| Maximum Operating Frequency | β | 100 MHz |
| Product Terms | β | 160 total |
| Dedicated Inputs | β | 4 |
| Total Input Pins | β | 20 |
| Supply Voltage | β | 5 V |
| Architecture | β | Turbo-only AND-OR-NOT, PAL-type |
| Technology | β | CMOS EPROM (UV-erasable / OTP) |
| Operating Temperature | β | -40C to +85C (industrial) |
| Programming Method | β | Altera programming hardware (UV erase for I grade, OTP for C grade) |
| TTL Emulation | β | 100% TTL compatible |