EP610DM-35 vs EP610IPC-10 비교
다음의 상세 나란히 비교: EP610DM-35 제조: Altera 및 EP610IPC-10 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP610DM-35 | EP610IPC-10 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $23.40 | $16.40 |
| Manufacturer | Altera (Rochester Electronics authorized stock) | — |
| Part Family | Classic EPLD | — |
| Logic Family | PAL-type EPLD, CMOS, UV-erasable | — |
| Number of Macrocells | 16 | — |
| Number of Gates | 300 | — |
| Propagation Delay (tPD) | 35 ns | 15 ns (commerical -10 grade) |
| Pipelined Data Rate (fMAX) | 100 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| 패키지 | 24-pin CDIP (CERDIP) with UV window | 24-pin PDIP (Plastic DIP) |
| Temperature Grade (M) | Military -55°C to +125°C | — |
| I/O Pins | 24 dedicated I/O (input + bidirectional) | 16 |
| Programmability | UV-erasable, reprogrammable | — |
| 동작 온도 범위 | -55°C to +125°C | — |
| MSL 레벨 | [DATA_NEEDED: MSL rating] | — |
| RoHS 상태 | Non-compliant (contains lead, hermetic CERDIP) | — |
| Family | — | Altera Classic EPLD |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Programmable Gates | — | 300 usable gates |
| Macrocells | — | 16 |
| Maximum Operating Frequency | — | 100 MHz |
| Product Terms | — | 160 total |
| Dedicated Inputs | — | 4 |
| Total Input Pins | — | 20 |
| 공급 전압 | — | 5 V |
| Architecture | — | Turbo-only AND-OR-NOT, PAL-type |
| Technology | — | CMOS EPROM (UV-erasable / OTP) |
| 동작 온도 | — | -40C to +85C (industrial) |
| Programming Method | — | Altera programming hardware (UV erase for I grade, OTP for C grade) |
| TTL Emulation | — | 100% TTL compatible |