EP610DM-35 vs EP610IPC-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP610DM-35 sa pamamagitan ng Altera at EP610IPC-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP610DM-35 EP610IPC-10
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Manufacturer Altera (Rochester Electronics authorized stock) —
Part Family Classic EPLD —
Logic Family PAL-type EPLD, CMOS, UV-erasable —
Number of Macrocells 16 —
Number of Gates 300 —
Propagation Delay (tPD) 35 ns 15 ns (commerical -10 grade)
Pipelined Data Rate (fMAX) 100 MHz —
Supply Voltage (VCC) 5 V (single supply) —
Packhaging 24-pin CDIP (CERDIP) with UV window 24-pin PDIP (Plastic DIP)
Temperature Grade (M) Military -55°C to +125°C —
I/O Pins 24 dedicated I/O (input + bidirectional) 16
Programmability UV-erasable, reprogrammable —
Hanay ng Temperature na Operasyon -55°C to +125°C —
Level ng MSL [DATA_NEEDED: MSL rating] —
Tindminan RoHS Non-compliant (contains lead, hermetic CERDIP) —
Family — Altera Classic EPLD
Device Type — EPLD (Erasable Programmable Logic Device)
Programmable Gates — 300 usable gates
Macrocells — 16
Maximum Operating Frequency — 100 MHz
Product Terms — 160 total
Dedicated Inputs — 4
Total Input Pins — 20
Volte ng Pagbibigay — 5 V
Architecture — Turbo-only AND-OR-NOT, PAL-type
Technology — CMOS EPROM (UV-erasable / OTP)
Temperature na Operasyon — -40C to +85C (industrial)
Programming Method — Altera programming hardware (UV erase for I grade, OTP for C grade)
TTL Emulation — 100% TTL compatible

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