EP610LC-25 vs EP610ILC-10 Comparison
Detailed side-by-side comparison of EP610LC-25 by Intel and EP610ILC-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610LC-25 | EP610ILC-10 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | UV-Erasable / OTP PLD |
| Family | Classic EPLD | — |
| Macrocells | 16 | 16 |
| Logic Array Blocks (LABs) | 4 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Toggle Frequency | 100 MHz | — |
| Pipelined Data Rate | Up to 100 MHz | — |
| Supply Voltage | 5 V ±5% | 5 V (single supply) |
| Technology | CMOS | — |
| Programmability | UV-erasable (windowed package) | — |
| Package | PLCC-28 | PLCC-28 (plastic J-lead chip carrier) |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Mounting Type | Surface Mount | Surface Mount (PLCC socket or solder) |
| I/O Pins | [DATA_NEEDED: exact I/O count] | 16 |
| RoHS Status | [DATA_NEEDED] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | Classic EPLD |
| Architecture | — | PAL-type with macrocells |
| Usable Gates | — | 300 |
| Product Terms | — | 160 |
| Dedicated Inputs | — | 4 |
| Pin-to-Pin Delay (tPD) | — | 10 ns (grade -10) |
| Counter Frequency (fCNT) | — | 100 MHz |
| Logic Family Compatibility | — | TTL (5 V CMOS/TTL-compatible I/O) |