EP610LC-25 vs EP610ILC-10 Comparación
Comparación detallada lado a lado de EP610LC-25 por Intel y EP610ILC-10 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP610LC-25 | EP610ILC-10 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $6,20 | $7,20 |
| Product Type | EPLD (Erasable Programmable Logic Device) | UV-Erasable / OTP PLD |
| Family | Classic EPLD | — |
| Macrocells | 16 | 16 |
| Logic Array Blocks (LABs) | 4 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Toggle Frequency | 100 MHz | — |
| Pipelined Data Rate | Up to 100 MHz | — |
| Tensión de alimentación | 5 V ±5% | 5 V (single supply) |
| Technology | CMOS | — |
| Programmability | UV-erasable (windowed package) | — |
| Encapsulado | PLCC-28 | PLCC-28 (plastic J-lead chip carrier) |
| Temperatura de funcionamiento | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Tipo de montaje | Surface Mount | Surface Mount (PLCC socket or solder) |
| I/O Pins | [DATA_NEEDED: exact I/O count] | 16 |
| Estado RoHS | [DATA_NEEDED] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | Classic EPLD |
| Architecture | — | PAL-type with macrocells |
| Usable Gates | — | 300 |
| Product Terms | — | 160 |
| Dedicated Inputs | — | 4 |
| Pin-to-Pin Delay (tPD) | — | 10 ns (grade -10) |
| Counter Frequency (fCNT) | — | 100 MHz |
| Logic Family Compatibility | — | TTL (5 V CMOS/TTL-compatible I/O) |