EP610LC-25 vs EP610ILC-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610LC-25 sa pamamagitan ng Intel at EP610ILC-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610LC-25 | EP610ILC-10 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | UV-Erasable / OTP PLD |
| Family | Classic EPLD | — |
| Macrocells | 16 | 16 |
| Logic Array Blocks (LABs) | 4 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Toggle Frequency | 100 MHz | — |
| Pipelined Data Rate | Up to 100 MHz | — |
| Volte ng Pagbibigay | 5 V ±5% | 5 V (single supply) |
| Technology | CMOS | — |
| Programmability | UV-erasable (windowed package) | — |
| Packhaging | PLCC-28 | PLCC-28 (plastic J-lead chip carrier) |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (PLCC socket or solder) |
| I/O Pins | [DATA_NEEDED: exact I/O count] | 16 |
| Tindminan RoHS | [DATA_NEEDED] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | Classic EPLD |
| Architecture | — | PAL-type with macrocells |
| Usable Gates | — | 300 |
| Product Terms | — | 160 |
| Dedicated Inputs | — | 4 |
| Pin-to-Pin Delay (tPD) | — | 10 ns (grade -10) |
| Counter Frequency (fCNT) | — | 100 MHz |
| Logic Family Compatibility | — | TTL (5 V CMOS/TTL-compatible I/O) |