EP610LC-30 vs EP610LC-35 Comparison
Detailed side-by-side comparison of EP610LC-30 by Intel and EP610LC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610LC-30 | EP610LC-35 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.40 | $9.95 |
| Family | Classic EPLD (EP610) | Altera Classic EPLD |
| Macro Cells | 16 | β |
| Logic Gates | Equivalent to 300 gates (typical) | β |
| Pin-to-Pin Delay (tPD) | 30 ns | β |
| Pipelined Data Rate | up to 100 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | β |
| Programming Voltage (VPP) | 13 V nominal | β |
| Technology | CMOS EPROM (UV-erasable) | CMOS EEPROM (one-time-programmable plastic) |
| Package | 24-pin CERDIP / PDIP | 28-pin PLCC (J-lead) |
| Operating Temperature | 0 C to +70 C (commercial) / -55 C to +125 C (military) | Commercial (0C to +70C) [DATA_NEEDED: exact grade letter] |
| Erase/Program Cycles | 1000 typical | β |
| Mounting Type | Through-Hole | Surface Mount |
| Output Type | CMOS tri-state (programmable) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs_status] |
| Logic Compatibility | TTL and CMOS | β |
| Turbo Mode | Yes (registered path bypass) | β |
| Device Series | β | EP610 |
| Macrocells | β | 16 |
| Usable Gates | β | 300 |
| Propagation Delay (tpd) | β | 37 ns |
| Supply Voltage (Vcc) | β | 5 V |
| Speed Grade | β | -35 (slowest EP610) |
| Programmable Pins | β | 24 input / 16 output (shared macrocells) |
| Lead-Free | β | [DATA_NEEDED: lead_free] |
| MSL Level | β | [DATA_NEEDED: msl_level] |
| Programming Tool | β | MAX+PLUS II development system |