EP610LC-30 vs EP610LC-35 比較
詳細な並列比較: EP610LC-30 メーカー: Intel および EP610LC-35 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP610LC-30 | EP610LC-35 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $16.40 | $9.95 |
| Family | Classic EPLD (EP610) | Altera Classic EPLD |
| Macro Cells | 16 | — |
| Logic Gates | Equivalent to 300 gates (typical) | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Programming Voltage (VPP) | 13 V nominal | — |
| Technology | CMOS EPROM (UV-erasable) | CMOS EEPROM (one-time-programmable plastic) |
| パッケージ | 24-pin CERDIP / PDIP | 28-pin PLCC (J-lead) |
| 動作温度 | 0 C to +70 C (commercial) / -55 C to +125 C (military) | Commercial (0C to +70C) [DATA_NEEDED: exact grade letter] |
| Erase/Program Cycles | 1000 typical | — |
| 実装タイプ | Through-Hole | Surface Mount |
| 出力タイプ | CMOS tri-state (programmable) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs_status] |
| Logic Compatibility | TTL and CMOS | — |
| Turbo Mode | Yes (registered path bypass) | — |
| Device Series | — | EP610 |
| Macrocells | — | 16 |
| Usable Gates | — | 300 |
| Propagation Delay (tpd) | — | 37 ns |
| Supply Voltage (Vcc) | — | 5 V |
| Speed Grade | — | -35 (slowest EP610) |
| Programmable Pins | — | 24 input / 16 output (shared macrocells) |
| Lead-Free | — | [DATA_NEEDED: lead_free] |
| MSLレベル | — | [DATA_NEEDED: msl_level] |
| Programming Tool | — | MAX+PLUS II development system |