EP610LC-30 vs EP610PC-30 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP610LC-30 disebabkan oleh Intel dan EP610PC-30 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP610LC-30 EP610PC-30
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete NRND
Family Classic EPLD (EP610) —
Macro Cells 16 —
Logic Gates Equivalent to 300 gates (typical) —
Pin-to-Pin Delay (tPD) 30 ns —
Pipelined Data Rate up to 100 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V 5 V (4.75 V to 5.25 V)
Programming Voltage (VPP) 13 V nominal —
Technology CMOS EPROM (UV-erasable) —
Kemasan 24-pin CERDIP / PDIP 24-pin PDIP (0.300 inch)
Suhu Operasi 0 C to +70 C (commercial) / -55 C to +125 C (military) 0C to +70C (commercial)
Erase/Program Cycles 1000 typical —
Jenis Pemasangan Through-Hole Through-Hole
Jenis Output CMOS tri-state (programmable) —
Status RoHS [DATA_NEEDED: RoHS status] Not applicable (legacy non-compliant package per distributor listing)
Logic Compatibility TTL and CMOS —
Turbo Mode Yes (registered path bypass) —
Device Family — Classic EPLD (EP610)
Macrocells — 16
Usable Gates — 300
Propagation Delay (tPD) — 30 ns
Maximum Pipeline Frequency — 33.3 MHz (typical) / 100 MHz pipelined
Process Technology — CMOS EPROM
Programmability — One-Time Programmable (OTP, no window on plastic PDIP)
Output Drive Current — [DATA_NEEDED: IOH/IOL per datasheet DC characteristics]
Input Pins (Dedicated) — [DATA_NEEDED: dedicated input count from datasheet pinout]
I/O Pins — [DATA_NEEDED: bidirectional I/O count from datasheet pinout]
Programming Tool — Altera A+PLUS / MAX+PLUS II (legacy)
Lead Free Status — Not applicable
Current Distributor — Rochester Electronics, LLC (authorized continuing source)

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