EP610PC-25T vs EP610PC-20T Comparison
Detailed side-by-side comparison of EP610PC-25T by Intel and EP610PC-20T by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP610PC-25T - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Intel / Altera
EP610PC-25T β Last Time BuySpecification Comparison
| Parameter | EP610PC-25T | EP610PC-20T |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $28.95 | $7.20 |
| Manufacturer | Intel (formerly Altera) | β |
| Distributor / Stocking Source | Rochester Electronics, LLC | β |
| Device Family | Altera Classic EPLD - EP610 | β |
| Device Type | Erasable Programmable Logic Device (EPLD, OTP for plastic package) | β |
| Logic Capacity | 300 usable gates | β |
| Macro Cells | 16 | β |
| Registers | 16 | β |
| User I/Os | 16 | β |
| Propagation Delay (tPD) | 25 ns (speed grade 25) | 20 ns |
| Maximum Toggle Frequency | [DATA_NEEDED: max fmax] | β |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Supply Voltage (VCC) | 5 V | 5 V |
| Process Technology | ECMOS (CMOS, EPROM-based) | β |
| Package | PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) | 24-pin PDIP (Plastic DIP) |
| Pinout Compatibility | Pin-compatible with EP610DC-25 (CERDIP-24, windowed) | β |
| Operating Temperature | 0 Β°C to +70 Β°C (commercial) | 0C to +70C (Commercial) |
| Programming Method | OTP (one-time programmable) via Altera programming hardware | β |
| Mounting Type | Through-hole | Through-Hole |
| RoHS Status | [DATA_NEEDED: RoHS status] | unknown |
| Shipping Form (T suffix) | Tube | β |
| Family | β | Classic EPLD |
| Logic Elements / Macrocells | β | 16 macrocells |
| Usable Gates | β | 300 gates |
| Maximum Frequency (fMAX) | β | 62.5 MHz |
| Number of Dedicated Inputs | β | 16 |
| Number of I/O Pins | β | 16 |
| Programmable Output Enable | β | Yes (per macrocell) |
| Programming Technology | β | UV-erasable EPROM, CMOS |
| Development Tool | β | MAX+PLUS II |