EP610PC-25T vs EP610PC-20T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610PC-25T sa pamamagitan ng Intel at EP610PC-20T sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP610PC-25T - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Intel / Altera
EP610PC-25T ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP610PC-25T | EP610PC-20T |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Manufacturer | Intel (formerly Altera) | — |
| Distributor / Stocking Source | Rochester Electronics, LLC | — |
| Device Family | Altera Classic EPLD - EP610 | — |
| Device Type | Erasable Programmable Logic Device (EPLD, OTP for plastic package) | — |
| Logic Capacity | 300 usable gates | — |
| Macro Cells | 16 | — |
| Registers | 16 | — |
| User I/Os | 16 | — |
| Propagation Delay (tPD) | 25 ns (speed grade 25) | 20 ns |
| Maximum Toggle Frequency | [DATA_NEEDED: max fmax] | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Supply Voltage (VCC) | 5 V | 5 V |
| Process Technology | ECMOS (CMOS, EPROM-based) | — |
| Packhaging | PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) | 24-pin PDIP (Plastic DIP) |
| Pinout Compatibility | Pin-compatible with EP610DC-25 (CERDIP-24, windowed) | — |
| Temperature na Operasyon | 0 °C to +70 °C (commercial) | 0C to +70C (Commercial) |
| Programming Method | OTP (one-time programmable) via Altera programming hardware | — |
| Uri ng Pagpapasok | Through-hole | Through-Hole |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | unknown |
| Shipping Form (T suffix) | Tube | — |
| Family | — | Classic EPLD |
| Logic Elements / Macrocells | — | 16 macrocells |
| Usable Gates | — | 300 gates |
| Maximum Frequency (fMAX) | — | 62.5 MHz |
| Number of Dedicated Inputs | — | 16 |
| Number of I/O Pins | — | 16 |
| Programmable Output Enable | — | Yes (per macrocell) |
| Programming Technology | — | UV-erasable EPROM, CMOS |
| Development Tool | — | MAX+PLUS II |