EP610PC-25T vs EP610PC-20T Comparación
Comparación detallada lado a lado de EP610PC-25T por Intel y EP610PC-20T por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EP610PC-25T - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Intel / Altera
EP610PC-25T ⚠ Última compraComparación de especificaciones
| Parámetro | EP610PC-25T | EP610PC-20T |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $28,95 | $7,20 |
| Manufacturer | Intel (formerly Altera) | — |
| Distributor / Stocking Source | Rochester Electronics, LLC | — |
| Device Family | Altera Classic EPLD - EP610 | — |
| Device Type | Erasable Programmable Logic Device (EPLD, OTP for plastic package) | — |
| Logic Capacity | 300 usable gates | — |
| Macro Cells | 16 | — |
| Registers | 16 | — |
| User I/Os | 16 | — |
| Propagation Delay (tPD) | 25 ns (speed grade 25) | 20 ns |
| Maximum Toggle Frequency | [DATA_NEEDED: max fmax] | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Supply Voltage (VCC) | 5 V | 5 V |
| Process Technology | ECMOS (CMOS, EPROM-based) | — |
| Encapsulado | PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) | 24-pin PDIP (Plastic DIP) |
| Pinout Compatibility | Pin-compatible with EP610DC-25 (CERDIP-24, windowed) | — |
| Temperatura de funcionamiento | 0 °C to +70 °C (commercial) | 0C to +70C (Commercial) |
| Programming Method | OTP (one-time programmable) via Altera programming hardware | — |
| Tipo de montaje | Through-hole | Through-Hole |
| Estado RoHS | [DATA_NEEDED: RoHS status] | unknown |
| Shipping Form (T suffix) | Tube | — |
| Family | — | Classic EPLD |
| Logic Elements / Macrocells | — | 16 macrocells |
| Usable Gates | — | 300 gates |
| Maximum Frequency (fMAX) | — | 62.5 MHz |
| Number of Dedicated Inputs | — | 16 |
| Number of I/O Pins | — | 16 |
| Programmable Output Enable | — | Yes (per macrocell) |
| Programming Technology | — | UV-erasable EPROM, CMOS |
| Development Tool | — | MAX+PLUS II |