EP610PC-25T vs EP610PC-20T Comparaison
Comparaison détaillée côte à côte de EP610PC-25T par Intel et EP610PC-20T par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP610PC-25T - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Intel / Altera
EP610PC-25T ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP610PC-25T | EP610PC-20T |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $28,95 | $7,20 |
| Manufacturer | Intel (formerly Altera) | — |
| Distributor / Stocking Source | Rochester Electronics, LLC | — |
| Device Family | Altera Classic EPLD - EP610 | — |
| Device Type | Erasable Programmable Logic Device (EPLD, OTP for plastic package) | — |
| Logic Capacity | 300 usable gates | — |
| Macro Cells | 16 | — |
| Registers | 16 | — |
| User I/Os | 16 | — |
| Propagation Delay (tPD) | 25 ns (speed grade 25) | 20 ns |
| Maximum Toggle Frequency | [DATA_NEEDED: max fmax] | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Supply Voltage (VCC) | 5 V | 5 V |
| Process Technology | ECMOS (CMOS, EPROM-based) | — |
| Boîtier | PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) | 24-pin PDIP (Plastic DIP) |
| Pinout Compatibility | Pin-compatible with EP610DC-25 (CERDIP-24, windowed) | — |
| Température de fonctionnement | 0 °C to +70 °C (commercial) | 0C to +70C (Commercial) |
| Programming Method | OTP (one-time programmable) via Altera programming hardware | — |
| Type de montage | Through-hole | Through-Hole |
| Statut RoHS | [DATA_NEEDED: RoHS status] | unknown |
| Shipping Form (T suffix) | Tube | — |
| Family | — | Classic EPLD |
| Logic Elements / Macrocells | — | 16 macrocells |
| Usable Gates | — | 300 gates |
| Maximum Frequency (fMAX) | — | 62.5 MHz |
| Number of Dedicated Inputs | — | 16 |
| Number of I/O Pins | — | 16 |
| Programmable Output Enable | — | Yes (per macrocell) |
| Programming Technology | — | UV-erasable EPROM, CMOS |
| Development Tool | — | MAX+PLUS II |