EP610PC-25T vs EP610PC-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610PC-25T sa pamamagitan ng Intel at EP610PC-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP610PC-25T - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Intel / Altera
EP610PC-25T ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP610PC-25T | EP610PC-25 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Manufacturer | Intel (formerly Altera) | — |
| Distributor / Stocking Source | Rochester Electronics, LLC | — |
| Device Family | Altera Classic EPLD - EP610 | Classic EPLD (EP610 series) |
| Device Type | Erasable Programmable Logic Device (EPLD, OTP for plastic package) | OT PLD, PAL-type, CMOS |
| Logic Capacity | 300 usable gates | — |
| Macro Cells | 16 | 16 |
| Registers | 16 | — |
| User I/Os | 16 | — |
| Propagation Delay (tPD) | 25 ns (speed grade 25) | — |
| Maximum Toggle Frequency | [DATA_NEEDED: max fmax] | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Process Technology | ECMOS (CMOS, EPROM-based) | — |
| Packhaging | PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) | PDIP-24 (0.3 inch, through-hole) |
| Pinout Compatibility | Pin-compatible with EP610DC-25 (CERDIP-24, windowed) | — |
| Temperature na Operasyon | 0 °C to +70 °C (commercial) | [DATA_NEEDED: operating temperature grade] |
| Programming Method | OTP (one-time programmable) via Altera programming hardware | EPROM (UV-erasable), via Altera programming hardware |
| Uri ng Pagpapasok | Through-hole | Through-Hole (DIP) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Shipping Form (T suffix) | Tube | — |
| Usable Gates | — | 300 |
| Propagation Delay (tpd) | — | 25 ns |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Technology | — | CMOS, EPROM (UV-erasable) |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 20 (bidirectional, JTAG-programmable OE per macrocell) |