EP610PC-25T vs EP610PC-25 तुलना
विस्तृत दोनों ओर की तुलना EP610PC-25T द्वारा Intel और EP610PC-25 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Intel
EP610PC-25T - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Intel / Altera
EP610PC-25T ⚠ अंतिम खरीदविशेषता तुलना
| पैरामीटर | EP610PC-25T | EP610PC-25 |
|---|---|---|
| ब्रांड | Intel | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | अंतिम बार खरीदें | Obsolete |
| Manufacturer | Intel (formerly Altera) | — |
| Distributor / Stocking Source | Rochester Electronics, LLC | — |
| Device Family | Altera Classic EPLD - EP610 | Classic EPLD (EP610 series) |
| Device Type | Erasable Programmable Logic Device (EPLD, OTP for plastic package) | OT PLD, PAL-type, CMOS |
| Logic Capacity | 300 usable gates | — |
| Macro Cells | 16 | 16 |
| Registers | 16 | — |
| User I/Os | 16 | — |
| Propagation Delay (tPD) | 25 ns (speed grade 25) | — |
| Maximum Toggle Frequency | [DATA_NEEDED: max fmax] | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Process Technology | ECMOS (CMOS, EPROM-based) | — |
| पैकेज | PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) | PDIP-24 (0.3 inch, through-hole) |
| Pinout Compatibility | Pin-compatible with EP610DC-25 (CERDIP-24, windowed) | — |
| ऑपरेटिंग तापमान | 0 °C to +70 °C (commercial) | [DATA_NEEDED: operating temperature grade] |
| Programming Method | OTP (one-time programmable) via Altera programming hardware | EPROM (UV-erasable), via Altera programming hardware |
| माउंटिंग प्रकार | Through-hole | Through-Hole (DIP) |
| RoHS स्थिति | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Shipping Form (T suffix) | Tube | — |
| Usable Gates | — | 300 |
| Propagation Delay (tpd) | — | 25 ns |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Technology | — | CMOS, EPROM (UV-erasable) |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 20 (bidirectional, JTAG-programmable OE per macrocell) |